In the recent advance in semiconductor technology, specifically in the very large scale integration (VLSI) technology, a prominent objective is to increase the density, and thus the number of memory cells on a semiconductor chip to reduce costs and to increase operating speed. In particular, there has been much development into non-volatile memory devices, i.e., a type of memory device that retains stored data even after power to the device has been turned off. One of such devices is an electrically programmable ROM (EPROM).
An EPROM implements non-volatile storage of data by using a storage transistor having a so-called floating gate. The floating gate is located between a control gate and substrate and unlike the control gate, the floating gate is not connected to a word, bit, or any other line; and therefore it "floats". The EPROM is programmed by injecting hot electrons into the floating gate to cause a substantial shift in the threshold voltage of the storage transistor. Under high gate and high drain voltages, electrons gain sufficient energy to jump the silicon-silicon dioxide energy barrier, penetrating the oxide and flowing to the floating gate, which is completely surrounded by an oxide layer. The injected electrons cause a 5 to 10 volt increase in the threshold of the device, changing it from an ON to an OFF state when a nominal 5 volt read voltage is applied to the control gate. That is, if the floating gate holds electrons, it is negatively charged.
In a process of fabricating an EPROM or a Flash Memory device, a conventional salicide (self-aligned silicide) process cannot be used. A salicide process is a process in which a sandwich of silicide on polysilicon approach is extended to include the formation of source and drain regions using the silicide. The effect of a salicide process is to reduce the additional layer interconnect resistance, allowing the gate material to be used as a moderate long-distance interconnect. The reason that a conventional salicide process cannot be used in the fabrication of EPROM or Flash Memory cells is that because of the small thickness of the sidewall dielectric spacer that is build on the floating gate, a short circuit frequently occurs between the floating gate and the source/drain regions. The short circuit or the formation of a silicide bridge destroys the functions of the memory cell.
The deficiency of a conventional salicide process when used in an EPROM or Flash Memory cell is illustrated in FIG. 1. A split-gate EPROM cell 10 is shown in FIG. 1 having a control gate 12, a floating gate 14, a sidewall spacer 16 of a dielectric material, a VSS source region 18, a drain region 20 in a semiconductor substrate 22. In a conventional EPROM or flash fabrication process, a VSS source region 18 is first formed in a semiconductor substrate 22. A thin layer of oxide 24 is then formed on the surface of the substrate 22 by either a thermal oxidation process or a deposition process. The layer of thin oxide 24 is also known as a tunneling oxide layer since it allows tunneling electrons to pass from the substrate 22 to the floating gate 14. A floating gate 14 of a conductive material such as polycrystalline silicon is then formed on the tunneling oxide layer 24. The pattern for the floating gate 14 is defined by a thick oxide layer which is formed like a LOCOS oxide 26.
After the floating gate 14 is covered by a layer of oxide material or "ONO spacer", i.e. oxide/nitride/oxide (ONO) material, a control gate 12 of a second conductive material is formed on top of the floating gate 14 and the dielectric "ONO spacer". In the next step of etching the sidewall spacer 16, a portion 28 of the floating gate 14 can be exposed, i.e. the conductive polycrystalline silicon exposed from under the dielectric material 26. Prior to the formation of a salicide process, a hydrofluoric acid (or B.O.E.) dip may be required in order to remove residual oxide in the silicide area. The portion 28 of floating gate 14 is therefore exposed more and more. This process leads to the formation of a silicide bridge (or a short circuit) between the floating gate 14 at portion 28 and the thin oxide area 32 on the VSS source junction 18.
It is therefore an object of the present invention to provide a single-side oxide sealed salicide process for the fabrication of EPROM or Flash Memory cells without the drawbacks and shortcomings of the prior art methods.
It is another object of the present invention to provide a single-side oxide sealed salicide process for the fabrication of EPROM or Flash Memory cells that does not have short circuit problems between the floating gate and the source/drain regions.
It is a further object of the present invention to provide a single-side oxide sealed salicide process for the fabrication of EPROM or Flash Memory cells that does not have silicide bridge formation by the addition of a photoresist layer prior to the etching of the sidewall spacer such that the oxide layer on top of the floating gate remains unetched.
It is still another object of the present invention to provide a semiconductor structure for an EPROM or Flash Memory cell that does not have silicide bridge problems.
It is yet another object of the present invention to provide an EPROM or Flash Memory cell that does not have short circuit problems by depositing an electrically insulating CVD oxide layer on top of the floating gate.